Abstract
Synchronous binary counters are fundamental building blocks in high-speed digital and mixed-signal systems, including time-to-digital converters (TDCs), frequency synthesizers, data converters, timing engines, and IoT edge processors. Conventional synchronous counters drive the clock network of all storage elements at every cycle even though higher-order bits toggle infrequently, leading to unnecessary dynamic power. In addition, serial carry or passtransistor gating structures introduce cumulative RC delay as the counter width increases. This work presents a Parallel Look-Ahead Tree with Integrated Clock-Gating Pulse Architecture (PLAT-ICPA) for a 16-bit synchronous counter in standard 90 nm CMOS. The proposed architecture combines a Symmetrical Parallel Look-Ahead Tree (SPLAT), a glitch-free local clock-gating cell (GCGC), and an area-optimized transmission-gate pulsed T-flip-flop (TGPTFF). SPLAT partitions the counter into four 4-bit nibbles and generates group toggle conditions hierarchically, reducing long serial dependency. GCGC suppresses unnecessary clock activity while preventing runt pulses, and TGPTFF integrates toggle behavior into the storage cell to avoid an external XOR stack. Simulation results obtained through Cadence Spectre for post-layout simulation with 1.2 V and 1 GHz show that the delay is 0.165 ns, the total power dissipation is 0.840 mW, the number of transistors is 442, the silicon layout area is 14.28 $\mu\text{m}^2$, and the Power Delay Product (PDP) is 0.138 pJ. The proposed design outperforms the existing AMCPG-TFF counter in terms of power (47.5%), propagation delay (34.0%), and Power Delay Product (72.4%).
Keywords: 90 nm CMOS, Cadence Virtuoso, Clock Gating, Look-ahead carry, Low Power VLSI, T-flip-flop.