Abstract
A low-phase-noise X-band Phase-Locked Loop (PLL) designed for advanced wireless communication systems, such as satellite communications, 5G/6G networks and millimeter-wave applications, is presented in this paper. Designed in 45 nm CMOS using Cadence, the PLL integrates a high-performance varactor-based Voltage-Controlled Oscillator to achieve superior frequency tuning and phase-noise performance. The architecture supports a wide frequency range of 8–12 GHz, suitable for X-band operation and is driven by a 125 MHz reference with a programmable division factor (N = 64–96), offering flexibility across various wireless platforms. The Phase-Locked Loop achieves a phase noise of – 104.05 dBc/Hz at a 1 MHz offset, ensuring signal integrity and spectral purity critical in densely packed wireless environments. Featuring a compact footprint and power-efficient design, the proposed system consumes only 9.6 mW and achieves a Figure of merit (FoM) of −161.35 dBc/Hz, making it highly suitable for portable and battery-powered applications. This implementation demonstrates a highly integrated, economical solution for high-frequency communication, offering enhanced stability, low jitter and low power consumption. The proposed PLL meets the growing demands of modern wireless infrastructure, where high data rates, frequency agility and low noise performance are essential for reliable and scalable system deployment.
Keywords: CMOS, High Frequency, Low Phase Noise, Varactor-Based VCO, X-Band.