Abstract
The research focuses on developing a low-power and area-efficient approximate Booth multiplier architecture that leverages dynamic truncation to optimize performance for high-speed error-tolerant applications. Key aspects of the research include the design and implementation of the proposed multiplier architecture, the development of dynamic truncation algorithms tailored for real-time input data, and the evaluation of performance metrics such as power consumption, area efficiency, and error tolerance. The study explores the principles behind dynamic truncation and its application in approximate multiplication, emphasizing the trade-offs between accuracy and speed. Key aspects of the research include the design and implementation of the proposed multiplier architecture, the development of dynamic truncation algorithms tailored for real-time input data, and the evaluation of performance metrics such as power consumption, area efficiency, and error tolerance. Through simulations and synthesis, the study assesses the effectiveness of the proposed approach in achieving high-speed operation while maintaining acceptable levels of accuracy. The results reveal significant variations in output error across the different multipliers, with the proposed architecture demonstrating the lowest error rate of 0.001. In comparison, the Carry Width multiplier exhibits the highest error rate of 0.03, indicating relatively poorer accuracy. The Vedic and Voltage Mode multipliers perform better, with error rates of 0.025 and 0.002, respectively. Notably, the Wallace Tree multiplier shows the second-lowest error rate of 0.0015. The findings of this research contribute to advancing the field of digital arithmetic circuits, offering a promising solution for high-speed computing applications with stringent power and area constraints.
Keywords: Approximate, Booth Multiplier, Dynamic Truncation, Low Power, Simulations.